1. Field of the Invention
The present invention generally relates to an embedded circuit structure, and more particularly, to a process of an embedded circuit structure.
2. Description of Related Art
Along with the increasing contact count and contact density of an integrated circuit chip, a circuit carrier for packaging the chip needs a higher contact density and a higher wiring density to suit the tendency. In addition to the circuit carrier for packaging the chip, the circuit carrier used by a motherboard of an electronic product also gradually tends to high wiring density design to suit the miniaturization and thin-shape trend of electronic products. Therefore, the demand on circuit carriers with high wiring density is gradually growing.
The fabrication way of a circuit carrier today basically includes laminating process and build-up process. In terms of laminating process, when a patterned circuit layer on the surface of a dielectric layer is completed, required patterned circuit layers and dielectric layers are laminated into a laminating structure, following by plating through-hole to connect the patterned circuit layers located at different levels. In terms of build-up process, patterned circuit layers and dielectric layers are sequentially formed over a substrate, and meanwhile, conductive vias for successively connecting the previous patterned circuit layer are simultaneously fabricated during sequentially fabricating the patterned circuit layers.
U.S. Pat. No. 5,504,992 discloses a wiring board fabrication process, wherein a photoresist pattern is respectively formed on a thin metal layer located on each surface of a carrier metal foil; then the carrier metal foil is taken as a plating seed layer and a wiring pattern is formed on parts of the carrier metal foil not covered by the photoresist pattern; thereafter, the photoresist pattern is removed; further, the above-mentioned two wiring patterns are respectively embedded in both surfaces of a same dielectric layer to form a laminating structure, following by forming through-holes in the laminating structure and plating the inner walls of the through-holes with conductive material to form conductive vias for connecting the above-mentioned two wiring patterns; finally, the carrier metal foils and the thin metal layers are removed, and only the dielectric layer, the wiring patterns embedded in both surfaces of the dielectric layer and the conductive vias for connecting the wiring patterns are remained.